1. Field of the Invention
The present invention relates to a solid-state image sensor, and more particularly, it relates to a solid-state image sensor comprising an impurity region receiving signal charges and extracting voltage signal.
2. Description of the Background Art
A solid-state image sensor comprising an impurity region receiving signal charges and extracting voltage signal is known in general, as disclosed in Japanese Patent No. 3263197, for example.
FIG. 24 is a sectional view showing the structure of an exemplary conventional solid-state image sensor structurally similar to that disclosed in the aforementioned Japanese Patent No. 3263197. FIG. 25 is a potential diagram of the exemplary conventional solid-state image sensor shown in FIG. 24. Referring to FIG. 24, the exemplary conventional solid-state image sensor comprises an n-type silicon substrate 101. A p-type well region 102 is formed up to a prescribed depth from the upper surface of the n-type silicon substrate 101. An N−-type transfer channel region 103 is formed on the surface of the p-type well region 102 for storing and transferring signal charges. A plurality of stages of transfer gate electrodes 105 and an output gate electrode 106 are formed on the transfer channel region 103 at a prescribed distance through a gate insulating film 104. The plurality of stages of transfer gate electrodes 105 are constituted of first- and second-layer transfer gate electrodes 105a and 105b respectively.
The first- and second-layer transfer gate electrodes 105a and 105b are provided adjacently to each other through insulating films 107 respectively. The output gate electrode 106 is provided adjacently to the final-stage first-layer transfer gate electrode 105a through a corresponding insulating film 107. The solid-state image sensor alternately applies two-phase clock pulse signals ΦH1 and ΦH2 to the respective transfer gate electrodes 105, as shown in FIG. 25. The solid-state image sensor is so formed as to transfer signal charges stored in the transfer channel region 103 to the region located under the output gate electrode 106 by vertically moving channel potentials in potential wells formed in portions of the transfer channel region 103 located under the transfer gate electrodes 105 respectively with the two-phase clock pulse signals ΦH1 and ΦH2. The solid-state image sensor applies a prescribed DC voltage VOG to the output gate electrode 106 for holding the output gate electrode 106 in an ON-state.
An N++-type floating diffusion region 108 is formed on the p-type well region 102 of the n-type silicon substrate 101 continuously with the transfer channel region 103, as shown in FIG. 24. This floating diffusion region 108 is formed to receive and store the signal charges output from the transfer channel region 103. An N++-type drain region 109 is formed on the p-type well region 102 of the n-type silicon substrate 101 to hold an N−-type channel region 110 between the same and the floating diffusion region 108. A reset gate electrode 111 is formed on the channel region 110 through the gate insulating film 104. The solid-state image sensor inputs a reset pulse signal ΦR in this reset gate electrode 111, for switching the reset gate electrode 111 between ON- and OFF-states. The floating diffusion region 108, the drain region 109, the channel region 110, the gate insulating film 104 and the reset gate electrode 111 constitute a rest MOS transistor for discharging unnecessary signal charges after extraction of a voltage signal Vout from the floating diffusion region 108. In other words, the solid-state image sensor is so formed as to discharge unnecessary signal charges from the floating diffusion region 108 to the drain region 109 through the channel region 110 located under the ON-state reset gate electrode 111 by inputting the reset pulse signal ΦR into the reset gate electrode 111 for bringing the same into the ON-state after extracting the voltage signal Vout from the floating diffusion region 108.
The floating diffusion region 108 is formed at a prescribed distance L from the output gate electrode 106. Thus, the capacitance between the floating diffusion region 108 and the output gate electrode 106 is reduced. An interlayer dielectric film 112 is formed to cover the second-layer transfer gate electrodes 105b, the insulating films 107, the output gate electrode 106, the reset gate electrode 111 and the gate insulating film 104. A contact hole 112a reaching the surface of the floating diffusion region 108 is formed in regions of the interlayer dielectric film 112 and the gate insulating film 104 corresponding to the floating diffusion region 108 respectively. A wiring layer 113 is formed to fill up the contact hole 112a while extending on the interlayer dielectric film 112. The wiring layer 113 is connected to a source-follower output amplifying circuit 114 (see FIG. 25). This source-follower output amplifying circuit 114 is provided for extracting the signal charges stored in the floating diffusion region 108 through the wiring layer 113 while amplifying the extracted signal charges and converting the same to the voltage signal Vout. The output amplifying circuit 114 outputs the converted voltage signal Vout.
The voltage of the signal extracted from the floating diffusion region 108 to the output amplifying circuit 114 varies with the total capacitance Cfd of the floating diffusion region 108. In other words, the voltage of the signal extracted from the floating diffusion region 108 to the output amplifying circuit 114 is reduced as the total capacitance Cfd of the floating diffusion region 108 is increased. On the other hand, the voltage of the signal extracted from the floating diffusion region 108 to the output amplifying circuit 114 is increased as the total capacitance Cfd of the floating diffusion region 108 is reduced. The total capacitance Cfd of the floating diffusion region 108 is expressed as follows:Cfd=Cd+C1+C2+Cg  (1)
In the above expression (1), Cd represents the capacitance between the floating diffusion region 108 and the p-type well region 102, and C1 represents the capacitance between the floating diffusion region 108 and the output gate electrode 106. Further, C2 represents the capacitance between the floating diffusion region 108 and the reset gate electrode 111, and Cg represents the capacitance between the floating diffusion region 108 and the output amplifying circuit 114.
In the exemplary conventional solid-state image sensor shown in FIG. 24, the capacitance C1 between the floating diffusion region 108 and the output gate electrode 106 is reduced through the prescribed distance L provided between the floating diffusion region 108 and the output gate electrode 106, while it is conceivably difficult to sufficiently reduce the total capacitance Cfd of the floating diffusion region 108 by simply reducing the total capacitance Cfd. Thus, it is difficult to sufficiently increase the voltage of the signal extracted from the floating diffusion region 108 to the output amplifying circuit 114, and hence it may disadvantageously be difficult to detect the signal extracted from the floating diffusion region 108 in the output amplifying circuit 114. Consequently, detection sensitivity for the output signal is disadvantageously reduced.